1. Field of the Invention
The present invention relates to a data processor and more particularly to a microprocessor for a 32-bit reduced instruction set computer.
2. Description of the Prior Art
A detailed description has already been given of a reduced instruction set computer (hereinafter called `RISC`) capable of executing instructions at high speed in Japanese Patent Laid-Open No. 49843/1988 as a priority claim of U.S. Ser. No. 896,156 filed by IBM of the United States on Aug. 18, 1986.
A complex instruction set computer (hereinafter called `CISC`) microprocessor tends to become complicated in hardware as the hardware-to-software transfer of its function escalates. On the other hand, the RISC microprocessor tends to become so architectured as to perform uncomplicated functions to increase the processing speed.
As the RISC, there is also a known primitive instruction set computing machine system (hereinafter called `PRISM`) for directly executing a primitive instruction set using its hardware in order to execute all the primitive instructions in one machine cycle.
On the other hand, the tendency is for the mainstream of microprocessor architecture to increasingly change in such a manner that the CISC is replaced with the RISC because the improvement speed in performance of the latter is faster than that of the former.
In some recent high-performance RISC microprocessor, a fixed length instruction, 32 bits in fixed length, has been adopted and this fixed length instruction can be executed in one machine cycle.
On the other hand, `IEEE International Solid-State Circuits Conference DIGEST OF TECHNICAL PAPERS, pp 54-55, 1989` disclose microprocessors developed by Intel of the United States in which the processing performance has been improved by expanding the bandwidth of the bus, a data width on an external bus connected to the memory being 64 bits. In other words, two 32-bit instructions are fetched by the microprocessor from the memory via the external 64-bit data bus in one cycle and the two instructions can simultaneously be executed when they are an integer instruction and a floating-point instruction. The integer and the floating-point instruction may simultaneously be executed by an integer unit and a floating-point unit in parallel.
The RISC processor disclosed in Japanese Patent Laid-Open No. 49843/1988 has the function of simultaneously executing two instructions. This processor is equipped with a first and a second execution unit, a first and a second instruction decode unit, an instruction buffer for fetching instructions from a memory and feeding the instructions to the first and the second instruction decode unit, a register file and the like. On receiving outputs from the register file, the first and the second execution unit are capable of simultaneously performing processes in parallel.
Japanese Patent Laid-Open No. 49843/1988 also discloses special status where two parallel instructions are non-executable simultaneously ((1) when the second instruction of the two parallel instructions needs the result of the first instruction, (2) when the two parallel instructions belong to the same category of instructions, (3) when one of the parallel instructions needs more cycles than the other, (4) when one of the parallel instructions needs both execution units, and (5) when the destination registers of the two parallel instructions are the same and when it is needed to prevent the two instructions from being executed disorderly by canceling one of the instructions), and further discloses countermeasures to be taken in the status described above (in the cases of (1), (2), code scheduling by a compiler should be used to deal with them. As the RISC processor has such primitive instructions and there are only a few instructions requiring a plurality of cycles, the cases of (3), (4) occur unfrequently. Moreover, exception processing hardware should be used to deal with the status (5)).